ADC STM32

1. Chapter 7
ADC, DAC, AND SENSOR INTERFACING
1

2. Microcontroller Connection to Sensor via
ADC
2

3. An 8-bit ADC Block Diagram
3

4. Resolution versus Step Size for ADC (Vref
= 5V)
n-bit Number of steps Step size
8 256 5V /256 = 19.53 mV
10 1024 5V /1024 = 4.88 mV
12 4096 5V /4096 = 1.2 mV
16 65,536 5V /65,536 = 0.076 mV
Note: Vref = 5V
4

5. Vref Relation to Vin Range for an 8-bit
ADC
Vref (V) Vin in Range (V) Step Size (mV)
5.00 0 to 5 5 / 256 = 19.53
4.00 0 to 4 4 / 256 = 15.62
3.00 0 to 3 3 / 256 = 11.71
2.56 0 to 2.56 2.56 / 256 = 10
2.00 0 to 2 2 / 256 = 7.81
1.28 0 to 1.28 1.28 / 256 = 5
1.00 0 to 1 1 / 256 = 3.90
Note: In an 8-bit ADC, step size is Vref/256
5

6. Vref Relation to Vin Range for an 10-bit
ADC
Vref (V) VinRange (V) Step Size (mV)
5.00 0 to 5 5 / 1024 = 4.88
4.96 0 to 4.096 4.096 / 1024 = 4
3.00 0 to 3 3 / 1024 = 2.93
2.56 0 to 2.56 2.56 / 1024 = 2.5
2.00 0 to 2 2 / 1024 = 2
1.28 0 to 1.28 1.28 / 1024 = 1.25
1.024 0 to 1.024 1.024 / 1024 = 1
Note: In a 10-bit ADC, step size is Vref/1024
6

7. ADC STM32
Formas de llamar el ADC:
● Polling
● Interrupción
● DMA
Tipo de conversión:
● Un solo canal
● Múltiples canales
● Un solo canal, múltiples muestras

8. /* USER CODE BEGIN 1 */
uint16_t AD_RES = 0;
uint8_t MSG[35] = {'0'};
/* USER CODE END 1 */
while (1)
{
HAL_ADC_Start(&hadc1);
HAL_ADC_PollForConversion(&hadc1, 1);
AD_RES = HAL_ADC_GetValue(&hadc1);
sprintf(MSG,"%drn", AD_RES);
HAL_UART_Transmit(&hlpuart1, MSG, sizeof(MSG), 100);
HAL_Delay(100);
/* USER CODE END WHILE */
Inicia la conversión
Polling (Bloquea)
hasta que termina
la conversión
Copia el resultado

9. A Simultaneous 2-bit ADC
9

10. ADC0848 Parallel ADC Block Diagram
10

11. MAX1112 Serial ADC Block Diagram
11

12. Successive Approximation ADC
12

13. Some of the STM32F4xx Registers
13
Offset Address Register
0x00 ADC_SR (Status Register)
0x04 ADC_CR1(Control Register1)
0x08 ADC_CR2(Control Register2)
0x0C ADC_SMPR1
0x10 ADC_SMPR2
0x4C ADC_DR (Data Register)

14. Simplified Block Diagram of STM32F4xx chip
14

15. RCC_APB2ENR (RCC APB2 peripheral clock enable
register) to enable clock to ADC
15
Bit 10 ADC3EN: ADC3 clock enable
This bit is set and cleared by software.
0: ADC3 clock disabled
1: ADC3 clock disabled
Bit 9 ADC2EN: ADC2 clock enable
This bit is set and cleared by software.
0: ADC2 clock disabled
1: ADC2 clock disabled
Bit 8 ADC1EN: ADC1 clock enable
This bit is set and cleared by software.
0: ADC1 clock disabled
1: ADC1 clock disabled

16. ADC sample time register (ADC_SMPR1)
to set sampling time
16
000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles

17. ADC sample time register (ADC_SMPR2)
to set sampling time
17
000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles

18. Control 1 (ADC_CR1) Register (Not all bits are shown)
18

19. ADC bit Resolution Selection in ADC_CR1 register
19
RES (bits 25-24) Description
0x0 12-bit result
0x1 10-bit result
0x2 8-bit result
0x3 6-bit result

20. Control R1 (ADC_CR1) Register bits for ADC Channel Selection
20
Bit Description
4-0
ADC Channel Input Selection
AWDCH[4:0] Port PIN Analog Input Channel
0x00 PA0 ADC AIN0
0x01 PA1 ADC AIN1
0x02 PA2 ADC AIN2
0x03 PA3 ADC AIN3
0x04 PA4 ADC AIN4
0x05 PA5 ADC AIN5
0x06 PA6 ADC AIN6
0x07 PA7 ADC AIN7
0x08 PB0 ADC AIN8
0x09 PB1 ADC AIN9
0x0A PC0 ADC AIN10
0x0B PC1 ADC AIN11
0x0C PC2 ADC AIN12
0x0D PC3 ADC AIN13
0x0E PC4 ADC AIN14
0x0F PC5 ADC AIN15
0x10 Temperature (internal) ADC AIN16
0x11 VREFINT (internal) ADC AIN17
0x12 VBAT (internal) ADC AIN18

21. Analog input pin assignment in STM32F4xx
21
I/O Pin ADC I/O Pin ADC
PA0 AIN[0] PC0 AIN[10]
PA1 AIN[1] PC1 AIN[11]
PA2 AIN[2] PC2 AIN[12]
PA3 AIN[3] PC3 AIN[13]
PA4 AIN[4] PC4 AIN[14]
PA5 AIN[5] PC5 AIN[15]
PA6 AIN[6]
PA7 AIN[7]
PB0 AIN[8]
PB1 AIN[9]

22. GPIO_MODER Register
22
Bits 2y:2y+1 MODERy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O direction mode.
00: Input (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode

23. ADC_DR (ADC Data Register) register holds conversion
result
23
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Regular data
These bits are read-only. They contain the conversion result from the regular channels.
The data are left- or right-aligned.

24. ADC_DR (DATA) Register has the result and can be Right
and Left Justified
24

25. ADC_CR2 (ADC Control 2) register
25
Bit 11 ALIGN: Data alignment
This bit is set and cleared by software. Refer to Figure 75 and Figure 76.
0: Right alignment
1: Left alignment
Bit 10 EOCS: End of conversion selection
This bit is set and cleared by software.
0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection
is enabled only if DMA=1.
1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.
Bit 1 CONT: Continuous conversion
This bit is set and cleared by software. If it is set, conversion takes place continuously until
it is cleared.
0: Single conversion mode
1: Continuous conversion mode
Bit 0 ADON: A/D Converter ON / OFF
This bit is set and cleared by software.
Note: 0: Disable ADC conversion and go to power down mode
1: Enable ADC

26. ADC_SR(ADC Status g) Register for End-of-Conversion
26

27. ADC_SR (Status) Register Bits
27
Bit Field Descriptions
5 OVR Overrun This bit is set by hardware when data are lost. This happens if we
do not read the result of the last conversion from the Data Register
(ADC_DR). It is cleared by software.
0: No overrun occurred
1: Overrun has occurred
1 EOC End of Conversion
0: Conversion not complete
1: Conversion complete
Writing a zero to this bit will clear it or by reading the ADC_DR register.

28. ADC Connection for Program 7-1
28

29. ADC common control register (ADC_CCR) register
29

30. ADC common control register (ADC_CCR) register
30
Bit Field Descriptions
22 TSVREF
E:
Temperature Sensor and VREINT Enable
This bit is set and cleared by software to enable/disable the temperature sensor
and the VREFINT channel.
0: Temperature sensor and VREFINT channel disabled.
1: Temperature sensor and VREFINT channel enabled.
23 VBATE:
VBAT
enable
VBAT enable
0: VBAT channel disabled.
1: VBAT channel enabled.
17:1
6
ADCPRE: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC. The
clock is common for all the ADCs.
00: PCLK2 divided by 2
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8

31. Thermistor Resistance vs. Temperature
Temperature ('C) Tf (K ohms)
0 29.490
25 10.000
50 3.893
75 1.700
100 0.817
31

32. Thermistor
(Copied from http://www.maximintegrated.com)
32

33. LM34 and LM35
33

34. Getting Data to the CPU
34

35. LM34/35 Connection to ARM and Its Pin
Configuration
35