uit95

1. Digital Electronics
Topic: Decoders

2. Decoders
 A decoder is a combinational logic circuit that converts a N-
bit binary code into M output lines such that only one output
line is activated for each one of the possible combinations of
inputs.
 In other words, we can say that a decoder identifies or
recognizes or detects a particular code.
 In its general form, a decoder has N input lines to handle N
bits and form one to 2N output lines to indicate the presence
of one or more N-bit combinations. Since each of N inputs
can be a 0 or a 1, there are 2N possible input combinations or
codes.

3.  For each of these input combinations, only one of the M outputs will be
active (HIGH), all other outputs will remain inactive (LOW). Some decoders
are designed to produce active LOW output, while all other outputs remain
HIGH.
 Some decoders do not utilize all of the 2N possible input codes. For
example, a BCD to decimal decoder has a 4-bit input code and 10 output
lines that correspond to the 10 BCD code groups 0000 through 1001.
Decoders of this type are often designed so that if any of the unused codes
are applied to the input, none of the outputs will be activated.
 A binary decoder is usually implemented as either a stand-alone integrated
circuit (IC) or as part of a more complex IC. Widely used decoders are often
available in the form of standardized ICs.

4. General Decoder Diagram

5. 2-to-4 Line Decoder
 2-to-4 line decoder has 2 inputs & 4 outputs.
 It uses all AND gates & the outputs are active-HIGH as AND gates give output only when both
inputs are HIGH.
 It is also referred to as 1-of-4 decoder, because only one of the four outputs is activated at one
time.
No. of inputs=N=2
No. of outputs=2N=4

6.  A & B are the two inputs whereas D0 through
D3 are the four outputs.
Truth Table
 The Boolean expressions for the four outputs are:-
D0 = A’B’ , D1 = A’B , D2 = AB’ & D3 = AB.

7. 3-to-8 Line Decoder No. of inputs=N=3
No. of outputs=2N=8
 The Boolean expressions for the eight outputs are:-
Y0 = X0’ X1’ X2’ , Y1 = X0’ X1’ X2 , Y2 = X0’ X1 X2’ , Y3 = X0’ X1 X2 , Y4 = X0 X1’ X2’ , Y5 = X0 X1’ X2 , Y6 = X0 X1 X2’ ,
& Y7 = X0 X1 X2.
 3-to-8 line decoder has 3 inputs & 8 outputs.
 It uses all AND gates, and therefore the outputs are
active-HIGH. For active-LOW outputs, NAND
gates are used.
 It is also called a binary-to-octal decoder because it
takes a 3-bit binary input code and activates one of
the eight (octal) outputs corresponding to that code.
 It is also referred to as 1-of-8 decoder because only
one of the eight outputs is activated at one time.

8. Truth Table
 Some decoders have one or more ENABLE inputs that are used to control the operation of the
decoder.For example, in a 3-to-8 line decoder, if a common enabled line is connected to the fourth
input of each gate , a particular output as determined by the X0, X1, X2 input code will go HIGH only
when ENABLE line is held HIGH. When the ENABLE is held LOW, however, all the outputs will be forced
to the LOW state regardless of the levels at the X0, X1 & X2 inputs. Thus, the decoder is enabled only
when the ENABLE is HIGH.

9.  IC-74138 is a 3-to-8 line decoder.

10. 4-to-16 Line Decoder
 4-to-16 line decoder has 4 inputs
and 16 outputs.
 It is also referred to as 1-of-16
decoder as because only one of the
sixteen outputs is activated at one
time.
No. of inputs=N=4
No. of outputs=2N=16

11. Truth Table
 IC-74154 is a 4-to-16 line decoder.

12. BCD-to-Decimal Decoder/4-to-10 Line Decoder
 BCD-to-decimal decoders consist of eight inverters and ten four-input NAND gates. The
inverters are connected in pairs to make BCD input data available for decoding by the
NAND gates. Full decoding of valid input logic ensures that all outputs remain off for all
invalid input conditions.
 The BCD-to-decimal decoder is also called a 4-to-10 line decoder or 1-of-10 decoder. It has
4 inputs & 10 outputs. Only one output line is active at a time.
 6 of the 16 input combinations are invalid & for input combinations that are invalid for
BCD none of the outputs will be activated.

13. Truth Table
 IC 7442 is a BCD-to-decimal decoder with active LOW inputs & outputs.

14. BCD-to-
7-Segment
Decoder/
Driver
BCD input
0 0 0 0
Decimal output
LED
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
 Electronic decoders are available in IC form.
 This decoder translates from BCD to decimal.
 Decimals are shown on an 7-segment LED display.
 This IC also drives the 7-segment LED display.
BCD-to-Seven Segment Decoder

15.  This type of decoder accepts the BCD code & provides outputs to energize seven segment
display devices in order to produce a decimal read out. Sometimes the hex characters A
through F may be produced.
 Each segment is made of a material that emits light when current is passed through it. The
most commonly used materials include LEDs, incandescent filaments & LCDs. The LEDs
generally provide greater illumination levels but require more power than that by LCDs.

16. Truth Table

17. Decoder Applications
 Decoders are used whenever an output or group of outputs is to be activated only on the
occurrence of a specific combination of input levels. These input levels are often provided by the
outputs of a counter or register.
 Decoders can be used as timing or sequencing signals to turn devices on or off at specific times,
because when the decoder inputs come from a counter that is being continually pulsed, the
decoder outputs will be activated sequentially.
 Decoders are widely used in memory systems of computers where they respond to the address
code from the central processor to activate the memory storage location specified by the address
code.
 Decoder is designed to be used in high-performance memory-decoding or data-routing applications
requiring very short propagation delay times.
 In high-performance memory systems, this decoder can be used to minimize the effects of system
decoding.
 When used with high-speed memories using a fast enable circuit, the delay times of these decoders
and the enable time of the memory usually are less than the typical access time of the memory. This
means that the effective system delay introduced by the decoder is negligible.