1. Wavelet Lifting on
Application Specific Vector Processor
David Barina Pavel Zemcik
Faculty of Information Technology, BUT, Czech Republic
September 17, 2013
David Barina, Pavel Zemcik (FIT BUT) Wavelet Lifting on ASVP September 17, 2013 1 / 13
2. Motivation
discrete wavelet transform (DWT)
compression, e.g. JPEG 2000, Dirac
lifting scheme is SIMD-friendly
feasible for embedded systems
evaluated on Application Specific Vector Processor (ASVP)
David Barina, Pavel Zemcik (FIT BUT) Wavelet Lifting on ASVP September 17, 2013 2 / 13
5. Lifting CDF 9/7
lifting scheme practically
s
(0)
l = x2l
d
(0)
l = x2l+1
d
(1)
l = d
(0)
l +α (s
(0)
l + s
(0)
l+1)
s
(1)
l = s
(0)
l +β (d
(1)
l + d
(1)
l−1)
d
(2)
l = d
(1)
l +γ (s
(1)
l + s
(1)
l+1)
s
(2)
l = s
(1)
l +δ (d
(2)
l + d
(2)
l−1)
sl = ζ s
(2)
l
dl = d
(2)
l /ζ
David Barina, Pavel Zemcik (FIT BUT) Wavelet Lifting on ASVP September 17, 2013 5 / 13
10. FPGA kit SP605
Figure : Xilinx Spartan-6 FPGA SP605 Evaluation Kit
David Barina, Pavel Zemcik (FIT BUT) Wavelet Lifting on ASVP September 17, 2013 10 / 13
11. ASVP platform
two C source codes (MicroBlaze + PicoBlaze)
accelerate operations on vectors of floats
Vector operations
VCOPY M0[i] ← M1[j]
VADD M0[i] ← M1[j] + M2[k]
VSUB M0[i] ← M1[j] − M2[k]
VMUL M0[i] ← M1[j] · M2[k]
VMAC M0[i] ← M3[l] + (M1[j] · M2[k])
VMSUBAC M0[i] ← M3[l] − (M1[j] · M2[k])
David Barina, Pavel Zemcik (FIT BUT) Wavelet Lifting on ASVP September 17, 2013 11 / 13
12. Evaluation
100n
1µ
10µ
100µ
10.0 100.0 1.0k 10.0k 100.0k 1.0M
seconds/sample
horizontal BCE
vertical
samples
horizontal CPU
David Barina, Pavel Zemcik (FIT BUT) Wavelet Lifting on ASVP September 17, 2013 12 / 13
13. Summary
two methods compared on ASVP platform
achieved speedup is up to 2.6×
next research: an adaptation to the 2-D wavelet transform
vectorisation µs/sample speedup
CPU horizontal 1.1 1.0
CPU vertical 0.8 1.4
BCE horizontal 0.4 2.6
David Barina, Pavel Zemcik (FIT BUT) Wavelet Lifting on ASVP September 17, 2013 13 / 13